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Performance Semi MIPS Rx000
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The Performance Semi / MIPS R3000 Processor
The first commercial MIPS CPU model, the R2000, was announced in 1985 as a 32-bit implementation. It was followed by the R3000, the first successful MIPS design in the marketplace with more than 1 million processors made. The R3000 was used in high-end UNIX computers by Siemens and DEC and in the Silicon Graphics SGI Personal IRIS 4D/20 graphic workstations. On this machines 3D sequences for movies like The Abyss, Jurrasic Park or Terminator 2 were rendered.
 
The R3000 has an interface to handle 3 coprocessors. Each coprocessor has a flag line connected with the CPU that can be tested and a conditional branch executed dependent on its value. Coprocessor instructions can be executed directly from the instruction stream.
Coprocessor 0 (CP0) is incorporated on the CPU chip and supports the virtual memory system and exception handling. It is also referred to as the System Control Coprocessor. CP1 is reserved for the floating point coprocessor. An FPU is mandatory for most R3000 systems. CP2 is available for specific implementations and is often used to accelerate memory access by connecting it to an R3020 memory buffer or an R3220 read/write buffer chip. Later versions of the R3000 (R3000A) had built in memory buffer circuitry.
 
Reference:  R3000 at SGIstuff  R3000 information (German)
Performance Semi PR3000-33PGC
Performance Semi PR3000-33PGC Top Side
PACEMIPS
PR3000-33PGC
9021 V2 USA
Performance Semi PR3000-33PGC Back Side
01155
42
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Core Frequency:33 MHz
Board Frequency:33 MHz
Data bus (ext.):32 Bit
Address bus:32 Bit
Transistors:110,000
Circuit Size:1.20 µ
Introduced:1988
Manufactured:week 21/1990
Made in:USA
Package Type:Ceramic
Goldcap
PGA-145
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Performance Semi PR3000A-33MQ160C
Performance Semi PR3000A-33MQ160C Top Side
PACEMIPS
PR3000A-33MQ160C
PERFORMANCE
9449 USA
Performance Semi PR3000A-33MQ160C Back Side
1092-R3000A
11045AC
INDY 9444
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Core Frequency:33 MHz
Board Frequency:33 MHz
Data bus (ext.):32 Bit
Address bus:32 Bit
Transistors:110,000
Circuit Size:1.20 µ
Introduced:1988
Manufactured:week 49/1994
Made in:USA
Package Type:Ceramic
QFP-132
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The MIPS R3010 FPU
The R3010 is the FPU for the MIPS R3000 CPU. It provides high-speed floating point capability for systems based on the R3000 CPU. The organization of the FPU architecture is similar to that of the R3000 CPU, and allows for optimization of both integer and floating-point performance.
 
The R3010 FPU connects seamlessly to the R3000 CPU via the R3000 coprocessor interface CP1, and since both units receive instructions in parallel, floating-point instructions can be initiated at the same single cycle rate as fixed-point instructions.
Performance Semi PR3010A-25PGC
Performance Semi PR3010A-25PGC Top Side
PACEMIPS
PR3010A-25PGC
9104 USA
Performance Semi PR3010A-25PGC Back Side
04235 02
1093
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Core Frequency:25 MHz
Board Frequency:25 MHz
Introduced:1990
Manufactured:week 04/1991
Made in:USA
Package Type:Ceramic
PGA-84
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Performance Semi PR3010-33PGC
Performance Semi PR3010-33PGC Top Side
PACEMIPS
PR3010-33PGC
9017 V2 USA
Performance Semi PR3010-33PGC Back Side
00881
29
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Core Frequency:33 MHz
Board Frequency:33 MHz
Introduced:1988
Manufactured:week 17/1990
Made in:USA
Package Type:Ceramic
PGA-84
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