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Sun Microsystems SuperSPARC II
  Sun Microsystems SuperSPARC II STP 1021APGA, 85 MHz
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The Sun Microsystems SuperSPARC II Processor
Sun SuperSPARC II
The SuperSPARC II, introduced in 1994, is an enhanced version of the SuperSPARC CPU. It maintains the foundation of the SuperSPARC architecture and incorporates a number of improvements. A second-level external cache controller, optional with the original SuperSPARC, is required with the SuperSPARC II design. The SuperSPARC II additionally supports dual-byte ordering as specified in the SPARC V9 architecture (thus being still 32-bit SPARC V8 compliant). Improvements include a streamlined integer pipeline, a redesigned FPU to offer better superscalar performance and a memory management unit with a TLB (translation lookaside buffer) for each of the on-chip caches.
Sun Microsystems SuperSPARC II STP 1021APGA, 85 MHz
Sun Microsystems SuperSPARC II STP 1021APGA, 85 MHz Top Side
STP1021APGA-85
-B6
9545
5673219
H245 9508778
SUPERSPARC TM
STP1021AGF
980
TAIWAN
(c)1991 TI
Sun Microsystems SuperSPARC II STP 1021APGA, 85 MHz Top Side
A 85 MHz SuperSPARC II on an SM81 MBus module (Sun part no. 501-2953)
 
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Core Frequency:85 MHz
Data bus (ext.):32 Bit
Address bus:32 Bit
Transistors:3,100,000
Circuit Size:0.80
Introduced:1994
Manufactured:week 45/1995
Made in:Taiwan
L1 Cache:20+16 KB
L2 Cache:1 -2MB ext.
CPU Code:Viking
Package Type:Ceramic
PGA-313
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